Prior art IGBTs having trench MOS cells designs as shown in FIG. 1 have a trench gate electrode 7 with a gate layer 70, which is electrically insulated from a p doped base layer 3, an n+ doped source layer 2 and an n− doped drift layer 5 by a gate insulating layer 72. The trench gate electrode 7 is arranged in the same plane and lateral to the base layer 3 and extends deeper into the drift layer 5 than the base layer 3.
With such trench gate electrode designs, the on-state losses are lower than for planar gate designs, because the trench design offers a vertical MOS channel, which provides enhanced injection of electrons in the vertical direction and suffers from no drawbacks from charge spreading (so called JFET effect) near the cell. Therefore the trench cells show much improved carrier enhancement for lower losses. Due to the vertical channel design, the trench offers also less hole drain effect (PNP effect) due to the improved electron spreading out of the MOS channel than for planar gate designs. At the bottom of the trench there is an accumulation layer, which offers strong charge enhancement for the PIN diode part. Hence wide and/or deep trenches show optimum performance. The trench design offers large cell packing density for reduced channel resistance. The trench design, however, suffers from lower blocking capability near the bottom corners of the trenches due to high peak electric fields. The trench design has a large MOS accumulation region below the trench gate and associated capacitance with difficulty to apply field oxide type layers in the trench for Miller capacitance reduction. Therefore, the prior art device as shown in FIG. 1 results in bad controllability and high switching losses. Furthermore, the high cell densities in trench designs will result in high short circuit currents.
In order to reduce above mentioned effects, the trench gate electrodes 7 have been made wide and deep, whereas the cells have to be made narrow, so that losses are reduced and short circuit current can be kept low. However, such trenches are difficult to process and will still suffer from bad controllability.
In a further prior art concept shown in FIG. 2, IGBTs having a pitched-trench gate electrode design has been applied, in which a MOS area is inserted between the cells. The two trench gate electrodes 7, 7′ are connected by a layer 700 made of the same material as the trench gate electrodes 7, 7′, thereby forming an area below, in which a part of the base layer 3 is arranged, but no source layer or contact of the base layer to the emitter electrode is available in this MOS area. However, such devices result in bad blocking properties and high switching losses due to slow field spreading from the pitched area during switching.
In another approach shown in FIG. 3, dummy trench cells 110 have been introduced into another prior art IGBT, in which active cells 100, 100′ and dummy cells 110 are arranged in an alternating manner. The base layer 3 and source layer 2 do not have a contact to the emitter electrode 9 in the dummy cell 110, However, similar problems to those mentioned for the pitched-trench design apply.
In U.S. Pat. No. 9,105,680 B2 (FIG. 4) another prior art IGBT having trench gate electrodes 7, 7′ is described. Between two active trenches 7, 7′ a dummy cell 110′ is arranged with a further source layer 20 connected to each trench gate electrode 7, 7′ and a further base layer 30 and a further enhancement layer 40 separating the further base layer 40 from the drift layer 5. In the central part of the dummy cell 110, a deep p well 8 is arranged, which is separated from the further base layer 3 by the further enhancement layer 40, which further enhancement layer 40 extends to the emitter sided surface of the device. On top of the p well 8, a thin, only 50 to 150 nm thick insulating film 77 is arranged. The insulating film 77 is covered by a grounded poly silicon plate 78, which is directly connected to the emitter electrode 9 at a recess of the top insulating layer. Due to the thin insulating film 77 the p well capacity is connected to the emitter electrode 9 via the grounded poly silicon plate 78, the switching capability can be improved. However, in the prior art device known from U.S. Pat. No. 9,105,680 B2 the accumulation of holes during turn-on switching in the dummy area results in an increase of the Miller capacitance with the consequent loss of turn-on controllability.
From WO 2013/004829 A1 and EP 2 523 217 A1 prior art IGBTs are known, which have a dummy cell, which is coupled to the emitter electrode by a polysilicon plate, which is connected to the emitter electrode and which is weakly coupled to a well by an insulating layer in between.
Although in EP 2 523 217 A1, the connection of the poly plate to the emitter electrode is claimed to be as well effective for controllability, on condition to have an oxide of at least 300 nm underneath the poly, the manufacturing process inherently limits the maximum oxide thickness to be manufactured in only one thermal oxidation.
Moreover in EP 2 523 217 A1, the polysilicon plate has a higher resistivity than the metal emitter electrode, which results in a lateral potential drop between the edge of the polysilicon plate and the metal electrode which may negatively influences the coupling effect and the electric field at the lateral edges of the polysilicon plate.